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9V POSITIVE EDGE TRIGGERED TIMEOUT PUBLICThis circuit monitors the input at connector K2. On a falling edge (K2 connected to Ground), a timer is started via a 555 IC in monostable configuration. Once the timer lapse (timeout), the output on... by johnthunder | updated September 24, 2021 |
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Resistor sorter V4 As Built PUBLICby johnthunder | updated September 24, 2021 |
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AND GATE USING BIPOLAR JUNCTION TRANSISTORS PUBLICby johnthunder | updated September 12, 2021 |