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I need to do a tehnology mapping (group gates and flip flops) given a D ff and a MUX. Now I know what FPGAs mean and I understand I need to group them so that they "fit" in the given cell. But if I have only a D ff in my cell doesn't that mean I can group only the gates that are connected to the ff? A little help would be great cause I tried looking over some tutorials but didn't understand much. https://i.stack.imgur.com/pSZds.jpg I need to group the ones above the logic cells any help please |
February 13, 2018 |
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