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Please see circuit https://www.circuitlab.com/circuit/7rrsdb/pp-6_7/

The text gives the voltages across the capacitors (C1, C2, C3, C4) as (45, 45, 15, 30). Following their logic, this is what I get as well by hand. In CircuitLab, however, I am getting (54,36,18,18). What's going on?

Ceq=20uF

qTot=20uF * 90 V = 1.8 mC

V1 = 1.8 mC / 40 uF = 45 V

How does CL get 56V?

Capacitors in CL are not the mathematically ideal components of zero effective series resistance (ESR) and infinite parallel resistance (i.e. zero leakage current) that your problem assumes.

CL places a very large but finite resistance across the capacitors.

If you replace each capacitor in your problem with this parallel resistance then you will get the same DC solution given by CL.

Which of course is of no help to you because it does not give you the answer you are expecting.

However, if you replace the DC voltage source with a

PWS(0,0, 1n,90)

source then if you run a Time Domain sim for say:

Start Time = 0

Stop Time = 1s

Time Step = 1m

then you will get the answer for your problem as originally defined.

This is because the voltages across the caps all start from zero and are then stepped from an ideal zero source resistance voltage source and the very large parallel resistances have such a long time constant with the caps that you don't see the voltages drooping or climbing as they very slowly discharge or charge to where the DC solution ends up.

If you then run the sim with:

Start Time = 0

Stop Time = 1e15

Time Step = 1e12

then you will see the time constant. So in one sim you can see the initial solution (the one you want) and the steady state (for the conditions imposed by CL) solutions.

See this thread for more information:

https://www.circuitlab.com/forums/support/topic/4eqt8q32/voltage-calculations/

:)