Forums » CircuitLab Support Forum

Hello, I've encountered an error in which a subcircuit in one project has incorrect DC simulation results. An example is in this public project: https://www.circuitlab.com/circuit/6778g7sfnj99/circuitlab-dc-sim-error/ The issue is specifically with the group of three subcircuits in the bottom right corner.

A screenshot showing the problem is here: https://i.imgur.com/yXGtJaF.png

The issue is with the top left circuit. The middle node vm1 is at 0 V so resistors R22 and R23 and both nonzero with 1 V across each yet the simulation shows them at 0 A. The other two circuits are included as reference.

If I copy and paste these circuits into a new project then it shows the correct results, so it seems that somehow something in this project is interfering with it (I have other separate subcircuits in that project).

My system info:

Chrome 85.0.4183.121

macOS Version 10.14.5

Any help would be appreciated. Thanks!

Hi @nzk, yes it seems like the incomplete differential pair might be causing the circuit to fail to converge properly.

When I ground the gates of M1 and M3, it fixes the issue and both R22 and R23 show 1 amp current.

(Unrelated, but I see that the orientation of M3 may be backwards: it currently has source on top and drain on bottom.)

Hi @mrobbins, thanks a lot for the quick response. Yes I had put in the differential pair as a visual reference and didn't bother giving the gates paths to ground (or checking the M3 connection) and I see that grounding those fixes it.

Since I'm not familiar with the simulation solving process, does every network variable and equation end up the same matrix regardless of it came from a subcircuit that looks isolated?

Yes, that's correct: the simulator does not currently partition the matrix, even if the subproblems are entirely isolated. Although partitioning might provide a performance boost, it's a relatively unusual use case to want to simulate completely isolated circuits at the same time, when you can just break those simulations onto their own schematic. (There are definitely cases where it's useful though! Just hasn't been common enough to choose to implement partitioning in the simulation engine, which is fairly complicated.)

But I think CircuitLab could do better at indicating to the user that there has been a convergence failure. I'll have to investigate this situation at a later date and see whether that was detected; thanks for providing an example.

I see, thank you for the information. It would be great if CircuitLab could improve its error reporting in general since I think that's been the biggest usability problem I've noticed with it. Thanks for the help!