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Unstable Simulation

In this circuit:

Q1/Q2 and Q3/Q4 are connected in parallel.

With Q3/Q4 removed and a t=1s step=0.5s simulation, the resulting plot is:

That is correct and expected output. With Q3/Q4 in place and a t=1s step=0.5 simulation, the result should be virtually identical. However, it takes a very long time (~ 10 minutes) and produces this mess:

Running a t=1s step=0.1 simulation on the exact same circuit produces:

Which is much closer to the correct results but still a little strange at the transition point.

J

by jasonc
July 16, 2012

Wow apparently I did not get enough sleep last night.

Simulations are DC Sweep on Vctl.V 0-12V. Step for plots is 0.5, 0.5, 0.1 respectively. And I made up the "t=1s" thing.

Also V(un13) is the OA3 output voltage, V(un14) is the OA2 output voltage.

Sorry about that. J

by jasonc
July 16, 2012

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