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I am about a day into playing with the simulator and seem to have bumped into the first convergence issue. I've been using the AD712 model that is available... no thought to debugging it yet, but this problem shouldn't be model alone.

https://www.circuitlab.com/circuit/k3q67a/problems/

Running Frequency domain simulation looking at the labelled nodes, R24 set to >~1.92M all seems to run fine. I'm interrogating the phase and gain at each of the nodes. However, below about 1.9M ohm, the gain plots go from ~0dbV gain in the low end to about -200dbV in a very nonlinear fashion.

Something appears to be breaking as the simulation time also seems to blow up - so likely a convergence issue... Any suggestions?

Should I change op-amp models? Try something else?

Although this does not directly address your problem, it may help because a convergence problem may not always be created by the thing you think you have changed.

Your circuit is complex and as such is much more likely to suffer convergence problems than if you were to simplify it or better still break it up into smaller chunks which you analyse separately.

You can considerably simplify your circuit for simulation without changing the functionality at all: CL opamp models draw zero quiescent and output load currents from the supply rails so all the 10R and 100nF supply decoupling components contribute absolutely nothing to the simulation other than wasting computation time.

You also do not need to use a separate voltage source for every supply pin:

About Wires and nodes

If you hover your mouse over the end of a lead of a component that you have placed on the schematic a large, light grey dot will appear right at the end of the wire.

That is the (only valid) connection point for that component lead. Also referred to as a Node:

https://www.circuitlab.com/docs/the-basics/#nodes

If you Left-click and hold on that grey dot then drag the mouse cursor, a wire will appear.

Drag it to the next node you wish to join.

If you need to turn a corner, let go and then repeat the process on the node dot at the end of the wire you have just drawn and drag at right angles.

Note that you can also join nodes just by attaching a label to a node and then attaching a new label with the same name to another node. Those two nodes are now connected exactly as if you has drawn a wire between them:

https://www.circuitlab.com/docs/the-basics/#named_nodes

You can also draw a wire by clicking on the "Wire" button on the left hand palette then left-click and drag and release on the schematic.

To repeat a placement press shift before you click on the component you wish to place.

However, you must be consistent in your labelling:

https://www.circuitlab.com/forums/support/topic/86m9393x/bug-report-inconsistency-in-using-net-label-as-a-voltage/

Note also that CL assigns arbitrary but sequential node names to unlabelled nodes.

This can lead to very confusing results where node names are used in expressions for arbitrary sources and plot expressions.

Suppose you have a circuit with 17 nodes then you replace a resistor with a piece of wire.

Your circuit now has only 16 nodes. Suppose the node you removed was Node17.

Suppose you then add a new component in a different location that then adds a new node (by inserting a resistor in a wire for example). The new node will be auto-labelled by CL as Node17.

If you now add the first resistor back in it's original location. The node that reappears will now be auto-labelled Node18 and not Node17 as it was originally.

More complex editing makes a more comprehensive mess of the CL assigned node names.

If you put node name labels on all the nodes you are interested in then they won't change numbering or flicker in and out of existence as you edit your circuit. They will then always be valid in your expressions.

You can set up explicit voltage sources for the power supplies in CL or create an implicit supply using a node or net name. For example, the +1V or +1 node label invokes an implicit 1V source: https://www.circuitlab.com/circuit/a5bzf7/good-netname-and-a-free-voltage-source/ However, in: https://www.circuitlab.com/circuit/96br67/bad-net-name/ CL throws an error because the explicit 1V source, V1, is then in parallel with the implied source created by the node label.

You could try a different opamp model or try this behavioural model:

https://www.circuitlab.com/circuit/g5k727/behavioural-opamp-02/

You can now replace all the voltage sources in that schematic using a CL parameters block. I just haven't time to go back and rework the example to show it that way.

Another thing to try is the rail-less version of the opamp model:

https://www.circuitlab.com/docs/circuit-elements/#opamp

Not expecting rework, just some suggestions. Yours are good ones. Thank you for taking the time .

The resistors and caps are to look into some large signal clipping in the transient response... but you are right they don't need to be there for freq response analysis... just didn't want to have to change schematic to rerun analysis.

Some reasons to run simulation. Learning, you don't know how to analyze, or to gather ideas about why real world circuits might be susceptible to real world tolerances, coupling or other disturbances. Often this involves adding some potential parasitic components or coupling to the sim. In my case, I added several potential areas for investigation and because of the feedback nature of a PID controller through a somewhat mysterious actuator/sensor it is not really helpful to break the loop apart and analyze separately. Ideally, we can probe enough and match response to real world measurements to have some confidence that we've built an effective model for the unknown element and can use it to build better controllers.

Your comments are helpful. I may be guilty of quick frustration with tools that are in a new and not quite proven state, but the ease of the user interface is huge advantage for us that get to simulations about 1 week a year. I think the value of online tools like this will become immeasurable - especially if you leverage a large community for continuous improvement.

Still confused about why the system analysis is breaking, but I will simplify some and keep at it for a bit to see if there is a break that gets around the instability.

"The resistors and caps are to look into some large signal clipping in the transient response... but you are right they don't need to be there for freq response analysis... just didn't want to have to change schematic to rerun analysis."

I get your comments and reasoning and - with good models - you would be quite right to look into the effects of parasitics and supply noise, CMRR etc., but the sad fact is that as I pointed out, CL opamp models do not model currents into or out of the supply pins.

At all.

So there is no point in adding the decoupling RC netowrks because there is nothing happening with them.

At all.

All the supply pins on CL opamp models do is define the +/- output swing limits.

This is true of some vendor spice models too but most good quality opamp spice models do model supply current behaviour but even then you need to investigate to see.

I'm not sure how well CL would support trying to import that level of complexity in a subcircuit model; I've not tried.

I am currently working on a set of models that do mimic more closely, real world opamp behaviours but they are a week or two away just yet.

Drop me an email if you want to know more.