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Can someone suggest why this switch isn't working? https://www.circuitlab.com/circuit/7j9teg/switch_test/ I can get the switch to work by simply shorting out the capacitor. If the cap is shorted, the switch opens and closes as expected in sync with the clock. But if the cap is left in the circuit, the voltage v1 stays at 1v constant. Any thoughts? Thanks.

The switch is working.

Here's why it appears not to be working.

At the start of the sim, C1 is already charged up to approximately 1V because the switch has a finite but large OFF resistance and the simulator assumes that the switch has been open circui and that 1V has been applied for an infinite time prior to the start of the sim at T=0.

So when the switch closes the voltage across C1 effectively does not change.

In fact, C1 also has a finite but large resistance in parallel with it so the OFF resistance of the switch and the parallel leakage resistance of C1 (which is many orders of magnitude greater than the 10k resistor, R1, which can therefore be ignored in this part of the discussion) form a potential divider. This is why the voltage across C1 is very, very slightly less than exactly the 1V of the source voltage.

You don't see any change in V(v1) during the switching cycle because when the switch closes for the first time V(v1) charges up to exactly 1V (because the switch ON resistance is zero, so there is then no potential divider).

When the switch opens again, C1 discharges down to very, very slightly less than 1V through the total resistance of the switch OFF resistance in parallel C1 leakage resistance. The time constant for this is many orders of magnitude greater than the switching period.

About switches in CL:

It is not clearly documented but switches in CL do not have an infinite OFF state resistance. This can lead to unexpected results.

For example, a DC plot of this circuit:

https://www.circuitlab.com/circuit/586t3d/voltage-controlled-switch-off-state-resistance-01/

with R1 removed from the circuit would show V(output) = 1V.

Here's why.

The resistance to ground at the Output node is infinite because it is an open circuit.

However, the switches in CL are not ideal. They have a very large but finite OFF resistance.

Therefore when operating into an open circuit load there would be no difference between the ON and OFF state voltages at the Output node.

The example demonstrates this using a DC Sweep probing V(output) with a Decade Sweep of the value of R1 (R1.R) from 1e12 to 1e18 at 10 points/Decade.

It can be seen that V(Output) = 0.5V when R1.R is equal to around 1e15 Ohms.

This is the undocumented OFF state resistance of the CL voltage controlled switch.

Note that if a CL voltmeter were to be connected in place of R1 then there would be a clear ON/OFF state difference because the CL Voltmeter has a user definable finite resistance with a default value of 1G.

About capacitors in CL:

From

https://www.circuitlab.com/circuit/7rrsdb/pp-6_7/

Capacitors in CL are not the mathematically ideal components of zero effective series resistance (ESR) and infinite parallel resistance (i.e. zero leakage current) that your problem assumes.

CL places a very large but finite resistance across the capacitors.

If you replace each capacitor in your problem with this parallel resistance then you will get the same DC solution given by CL. Which of course is of no help to you because it does not give you the answer you are expecting.

However, if you replace the DC voltage source with a

PWS(0,0, 1n,90)

source then if you run a Time Domain sim for say:

Start Time = 0

Stop Time = 1s

Time Step = 1m

then you will get the answer for your problem as originally defined.

This is because the voltages across the caps all start from zero and are then stepped from an ideal zero source resistance voltage source and the very large parallel resistances have such a long time constant with the caps that you don't see the voltages drooping or climbing as they very slowly discharge or charge to where the DC solution ends up.

If you then run the sim with:

Start Time = 0

Stop Time = 1e15

Time Step = 1e12

then you will see the time constant. So in one sim you can see the initial solution (the one you want) and the steady state (for the conditions imposed by CL) solutions.

See this thread for more information:

https://www.circuitlab.com/forums/support/topic/4eqt8q32/voltage-calculations/

https://www.circuitlab.com/circuit/vv9ruy/capacitor-voltage/

DC voltage report is 33V/66V at a/b I calculate 54V across C1, 27V across C2, 18V across c3.

If CL applies the same sort of techniques as SPICE then CL probably places a very high value resistor in parallel with a capacitor as part of the model. This resistance will be somewhere between 1G (1e9) and 100T (1e14) Ohms.

Call it Rpar.

Rpar will be the same across each capacitor irrespective of value.

Hence the DC solution is correct.

Here's a proof:

https://www.circuitlab.com/circuit/nt8z84/finding-the-parallel-resistance-across-cl-capacitors-01/

The original circuit has been deleted and without it this thread is hard to understand.

Here's something that makes sense of it all again:

https://www.circuitlab.com/circuit/wjcgbv/capacitors-in-series-with-dc-supply-01/

Note that this is a poorly conditioned circuit and even if the parasitic resistance across the caps were to be infinite, in practice you would not realistically expect to find the voltages as calculated unless the initial voltage across them was zero and the supply was ramped up from zero.

Any practical attempt to measure the voltages of course would set up a leakage current which would alter the charge on the caps which would effectively give a zero voltage reading after more than a few time constants.

The time constant here would be due to the effective series capacitance seen across the measurement instrument terminals to ground and the resistance of the measurement instrument.

Ah, great feedback. Thanks!