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"Digital Clock" is out of sync when doing "Time Domain -> Sweep Parameter".

See: https://www.circuitlab.com/circuit/kxn78q6zj7ch/clock-sweep-bug/

From the "Transient Analysis" it can be seen that the digital clock triggers late (inverse duty cycle maybe?) on the second run.

Some duty cycles give correct results (e.g. 0.6, 0.7) others give incorrect results (e.g. 0.1, 0.2, 0.5, 0.9).

Firefox 82.0.2 - Chrome 83.0.4103.61 - Arch Linux 64bit

Hi @xenris, thanks for the bug report!

We've just fixed it. The simulation engine now properly resets digital clock state between parameter sweep runs.

(If you have an editor window open, just save your work and refresh your CircuitLab browser tab and you'll be running the updated code.)