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In circuit camparator_Fails? I have ac source on one side of capacitor And dc offset on other side, but circuits sees ac with no offset. I want to run 0.5 V AC into either comparator or logic with threshold at 2.5 V to get output timed at zero crossings.

@detector,

When asking for help about a particular circuit in CL, it is good practice to include a link to a public copy of that circuit so that others can see and therefore offer suggestions on it.

Like this:

https://www.circuitlab.com/circuit/8dervk/comparator_fails/

It saves everyone having to find it from your own workbench.

:)

Unless you have edited your circuit since you posted this question, the simulation appears to be doing exactly what you would expect.

Both comparator inputs are at 2.5V one through V2 directly, the other through R2.

If you set Skip initial = No then at the start of the simulation, CL assumes that the DC conditions at t = 0 have existed for all time t < 0 so the DC voltage across C1 is at it's steady state of 2.5V. Therefore the comparator sees both inputs at a mean DC level of 2.5V so the comparison takes place at the 50% points of the sinusoid.

If you set Skip initial = Yes then at the start of the simulation, CL assumes that the DC voltage across C1 is at an initial voltage = 0. Therefore the comparator sees the inverting input held at 2.5V and the other inputs at a mean DC level of 0V so the comparison takes place at the 75% points of the sinusoid.

If you run the sim for long enough (or make C1 smaller: try 10nF) you will see the mean DC level of the signal at the non-inverting input of the comparator (NODE3) climbing towards 2.5V with an RC exponetial time constant of C1R2.

Thanks, I was not paying attention to the skip initial.