Hi everyone I'm a student in 2nd year of Classe Preparatoire in France and I have to create a VCO for a Phase-locked loop I made this circuit in class http://www.circuitlab.com/circuit/5g296u/vco/ the voltage after the first and the second OA must be symetric but it doesn't, that's why I want to simulate it. However my circuit on the website doesn't start, I think I need to make an initial condition on my capacitor to make the oscillator start but I searched on the forum and I didn't understand how to do it Original page of the VCO with the graphics I should have : http://www.esiee.fr/~poulichp/PR201/VCO/VCO.html (bottom of the page) Thanks in advance Dimitri |
by Dimfougne
May 28, 2013 |
Hi again, I didn't find how to edit my last message, here are the photo of the oscilloscope of my circuit for a voltage in enter of 3V : http://imageshack.us/photo/my-images/208/photo1wub.jpg/ and here's the graph of the theory (taken from an other website : http://www.esiee.fr/~poulichp/PR201/VCO/VCO.gif ) |
by Dimfougne
May 28, 2013 |
This should fix it: See also: https://www.circuitlab.com/circuit/b24363/ramped-and-glitched-signals-and-supplies-01/ :) |
by signality
May 28, 2013 |
Hi signality, thanks for your answer the circuits works very well ! I have a question why did you put a exponentional ramp-up voltage on the positive and negative power supplies of the OAs ? The goal is to delay the start of the oscillator to charge the capacitor ? Moreover have you got an idea of the cause of the phenomenon that I have in reality ? Here are pictures of the oscilloscope -if Ve=2.5V : http://imageshack.us/a/img197/7336/photo1j.JPG -if Ve=5V : http://imageshack.us/a/img593/6356/photo2kzv.jpg -if Ve=7.5V : http://imageshack.us/a/img17/5219/photo3wi.jpg Thank you very much for giving me your time. Dimitri. |
by Dimfougne
May 29, 2013 |
Hi Dimitri, "why did you put a exponentional ramp-up voltage on the positive and negative power supplies of the OAs ?" It's actually only on the +ve supply but no matter. It's to kick the circuit into oscillation from an initial, possibly metastable state. Have a read through these for more info and examples: https://www.circuitlab.com/browse/by-tag/initial-conditions/ |
by signality
June 01, 2013 |
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