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Hi, when looking at this voltmeter in the time domain I see the voltage initially starts rising at 4 seconds. The square wave is set to 0.1 Hz and should thus start rising at 5 seconds with 180 degrees phase shift. What am I missing here? And how is it possible this voltage is negated? (Don't mind the closed switch)

Thanks!

Two questions and a couple of comments:

Questions:

i) why have you shorted out the buffer? Try removing the net connecting input to output.

ii) why do you think there is a 180 degree phase shift when you are using a non-inverting buffer?

Comments:

a) Your time step is set to 1s so things can only happen in 1s steps. Reduce the size of the time step to see higher time resolution.

b) it helps if you label your nets: CL is not good at telling the viewer where V(un3) actually is.

i) The shorted buffer is the reason I'm doing the simulation. I wanted to see if it latched and kept being in high state when the input signal went low again.

ii) The 180 deg phase shift is not really a phase shift, but the signal phase is input to 180 degrees because I wanted the signal to start out low, then shift to high.

a) this was the solution! Don't know why though. The signal should not switch to high right BEFORE it's supposed to, rather after. I think at least.

b) thank you for commenting. I usually label my circuits very well. I didn't think it would matter much in this case. But as always, the answer always go past my initial expectations of a solution, so then the other nets matter.

Think I get the hang of it now.

You should probably add some series R to the voltage source or between input and output of the buffer so that the switched voltage source doesn't directly short the buffer output when it is connected to the buffer input.

:)

You've got an irresistible force pushing against an immovable object. When the square-wave goes high, the buffer output is low. Neither the generator nor the buffer have a spec for their output impedance, so you have to assume they're both zero. Strictly speaking, you're going to have infinite current flowing, with the generator trying to put out volts, and the buffer holding the node low.

CL can't come up with a reasonable answer for this scenario.

One solution is to make the circuit a bit more realistic, with small resistors on the generator and the buffer output.

Logic elements in CL - of which your buffer is one - do have a 10R output resistance so they can't pull as hard as the ideal voltage source yo're driving it from (noting that your switch, SW1, has zero on resistance R_ON=0).

https://www.circuitlab.com/docs/circuit-elements/#digital

Even so @arduinohacker is describing in a bit more detail the point I was making about adding some R in series with the source and/or in the feedback loop. One or the other or both of what I've illustrated here:

In fact, with a 10R buffer output resistance, you really only have one option: add Rfb1. If you leave the feedback directly connected then Rser1 has to be much less than 10R so you are still stressing the buffer output stage when you close the switch (at least until the buffer flips to the same level as the input).

With Rfb1, you don't need Rser1 to protect the output but it is probably good practice to include it just to offer a little more protection of the buffer input by increasing the source resistance of any potential ('scuse the pun) ESD source.

BTW: in the example above I've added netnames and reduced the clock period, simulation and step times so that you can see the buffer propagation delay and hence the behaviour of the swin net due to the potential divider formed between Rfb1 and Rser1.

In practice you would use much lower resistors if you wanted to clock things that fast!

I've also offset the clock so that it no longer has a +/-5V swing! A real buffer would be very unhappy with that.

:)

Hate that all my digital problems go analog when I cry for help. Oh well :) Thanks for helping out guys, appreciate it very much.

What example are you referring to, @signality? All I really wanted to do was to make an easy latching output, hehe. Trying out only Rfb and Rser with different values. Also set amplitude 2.5 v with 2.5v offset for the looks. Not seeing much difference, I guess then my idea was not very clever in the first place!

If I wanted to make a digital pattern to simulate different output combinations of my regenerated RF signals from my RF module, must I then "program" it myself using different clocks and digital parts to make a combination? I want to draw the digital signal like in fpga simulation...

Sorry! Forgot to post the link:

The easiest way to generate an arbitrary digital pattern in CL is to use the PWS() source.

For info:

https://www.circuitlab.com/docs/expressions/

Here's an example:

It shows some other features of using one of these sources as part of a more complicated arbitrary source expression but you should be able to get the basic idea from there.