MOSFET (CMOS) NOR gate

Two n-channel MOSFETs and two complementary p-channel MOSFETs form a two-input CMOS NOR logic gate.

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When in_A or in_B are high, the output voltage is pulled low via M1 and/or M2. Otherwise, the output voltage pulled high via M3 and M4.

Load the simulation by clicking "Open in editor" above, and then click "Simulate" at the bottom. Run a time domain simulation.

Plot the voltages at nodes in_A, in_B, and out versus time. You should verify that the logic performs the correct operation.

How much current is consumed? Compare to the MOSFET-and-resistor versions of the gate (see below).

MOSFET (CMOS) NOR gate PUBLIC