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Created | August 14, 2020 |
Last modified | September 07, 2020 |
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First attempt at simulating a Ge PNP transistor. Mainly concentrating on the low voltage Vbe junction.
Experimental work This model has had very limited evaluation and might not work outside a modest specification: beta 100, Ic 5mA, Vce -1.5V, frequency 10kHz, Vbe negative only, Emitter 0V only.
Model. This circuit owes its origins to the technique of current mirrors which link BJTs at the base. For example:- https://www.circuitlab.com/circuit/7f7ge4/bjt-current-mirror/ . This model translates base voltages (at V2) from a "Ge-type" pn junction to those of a Si junction.
Ge-Si Vbe. The voltage multiplier V2 uses an approximate formula to scale from Ge levels of Vbe up to Si levels. Accuracy is limited, in part, by my lack of understanding of SPICE models. Two numbers in element V2 are important:-
D1, D2 have low junction voltages but I don't know the substrate material. (For information: "EG" is the SPICE model parameter for band gap, default value 1.1eV for Silicon.)
Base/input. D1 and D2 separate the base and emitter currents of the Ge BJT simulation. This simplifies the simulation. Attempt at fidelity by feedback to V3 so that external Vbe matches D2. D3 blocks in-flowing base currents.
Miller. C1 supplies Q1's "output" capacitance, the one responsible for the Miller effect. The zero impedance voltage source V2, at Q1 base, puts Q1 in common base mode which almost eliminates collector-base feedback.
beta. Nominally 100. DC Sweep gives a range of 91.7 - 89.7 over Ic range 600uA to 1.18mA.
Biasing. R1,R2 bias Q1 to a collector voltage near to half the supply, for testing by the DC Solver.
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