| Created by |
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| Created | May 16, 2012 |
| Last modified | May 16, 2012 |
| Tags | sample-and-hold track-and-hold |
A simple behavioural track and hold circuit.
V(track) = 1 => V(out) tracks V(in)
V(track) = 0 => V(out) held at value of voltage across Chold1 when V(track) 1 => 0 edge.
Vilim1 sets the current limit available to charge and discharge the hold capacitor Chold1.
VCVS1 buffers the voltage across Chold1.
Not provided.
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