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Created | September 02, 2013 |
Last modified | September 02, 2013 |
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Simple Tremolo circuit using an N channel JFET as a voltage controlled resistor.
Simple Tremolo circuit using an N channel JFET as a voltage controlled resistor.
A reduced signal distortion and larger gain swing version of:
https://www.circuitlab.com/circuit/a78uqj/tremolo/
Split gate bias resistors reduces signal distortion:
http://www.vishay.com/docs/70598/70598.pdf
https://www.circuitlab.com/circuit/y86grn/voltage-controlled-attenuators-using-jfets-01/
Note that gate bias voltage is with respect to vcc.
See also:
https://www.circuitlab.com/circuit/a6hr4e/tremolo-03/
https://www.circuitlab.com/circuit/dn9sbn/tremolo-04/
Simulate > Time Domain > Run Time-Domain Simulation
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